1. Technical Field
The present invention relates to apparatus and methods for writing a selected bit of a word into a random access memory (RAM) having a prescribed number of bits defining a word length.
2. Background Art
Memory architectures are typically configured to store a prescribed number of words having a predetermined word length. Such memory structures, known as word organized arrays, have a prescribed number of columns and rows, where the column length (i.e., the number of rows) equals the number of words, W, and the row length (i.e., the number of columns) equals the number of bits per word. Word selection is thus performed using a one-out-of-W decoder. i.e., a decoder with a mutually exclusive output for each word in the memory. The address inputs to the decoder select one and only one of the decoder's outputs, thus selecting one word in the memory array. Address decoder size may be reduced using two-level decoding, where one level corresponds to a physical word and another to a logical word, such that the physical word consists of the number of bits in a row of the memory array, and the logical word consists of the number of bits of a physical word which are sensed and gated to the output at one time.
Hence, the reading and writing of data to and from a memory array involves addressing a word of memory based on its corresponding address, and reading and/or writing the word having the prescribed number of bits from the memory array.
Applications using random access memories for storing configuration data may store multiple configuration parameters within a single data byte. For example, a configuration word may be stored as a single byte (8-bits) having multiple fields of one or more bits. For example, a word may have eight 1-bit configuration values, requiring external logic to ensure that selected bits of a stored word are not overwritten.
Hence, resetting a bit of a configuration word stored in memory must typically be performed on a per-byte basis, where a selected bit is reset by addressing the word, reading the contents from memory, modifying the contents of the retrieved data word using external logic, and rewriting the modified word back into memory. Thus, this read-modify-write technique requires at least three clock cycles to modify a single bit in the memory configured for reading and writing on a per-byte basis, and requires additional external logic that increases the size and cost of the IC chip.